1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more specifically to, for example, a structure of a scribe line area in an integrated circuit and a manufacturing method thereof.
2. Description of the Background Art
FIGS. 23 to 26 are schematic cross-sectional views that show a sequence of processes of a manufacturing method of a conventional semiconductor device, for example, described on page 107 in xe2x80x9cMonthly Semiconductor Worldxe2x80x9d, December Issue, 1997. Referring to FIG. 23, a resist pattern 120 is formed on an insulating film 102 by a photolithographic technique. This insulating film 102 is subjected to a reactive ion etching process by using this resist pattern 120 as a mask. Thus, a groove 102a is formed on the insulating film 102. Thereafter, the resist pattern 120 is removed by ashing and a chemical treatment.
Referring to FIG. 24, a TaN film is formed on the insulating film 102 having a groove 102a as a barrier metal 114 with a thickness of 50 nm, and a Cu film is further formed thereon with a thickness of 150 nm as a seed layer 112a for a plated film.
Referring to FIG. 25, in a plating liquid of a copper sulfate bath, an electrolytic plating process is carried out so that the groove 102a is filled with the Cu film 112. Thereafter, the Cu film 112 and the barrier metal 111 are abraded and removed by a chemical and mechanical polishing method (CMP method), until at least the upper surface of the insulating film 102 has been exposed.
Referring to FIG. 26, by this CMP method, the Cu film 112 and the barrier metal 111 remain only in the groove 102a to form wiring.
FIG. 27 is a schematic cross-sectional view that shows the structure of an electrolytic plating device, for example, shown on page 470 of xe2x80x9cProc. Of 1993 VLSI Multilevel Interconnection Conferencexe2x80x9d. Referring to FIG. 27, the electrolytic plating is carried out by applying a voltage between an anode 132 and a wafer 110 that are placed in an electrolytic solution 135 in a plating vessel 133; thus, a Cu film is deposited on the wafer 110 side. Here, the electrolytic solution 135 is introduced into the plating vessel 133 from an electrolytic solution inlet 134, and discharged from an electrolytic solution outlet 136.
On the wafer 110, the barrier metal 111 and the seed layer 112a have been formed on the insulating film 102, and the plated Cu film is deposited on the seed layer 112a. Here, the insulating film 102 is formed on, for example, a semiconductor substrate 103.
Moreover, the voltage to be applied to the wafer 110 is supplied to the barrier metal 111 and the seed layer 112a on the surface of the wafer 110 through a contact electrode 131. At this time, the deposition of the plating film preferentially takes place in the groove and on the bottom of the hole because of the effects of an additive agent added to the electrolytic solution 135 so that it is possible to obtain a superior filling property. Since such a phenomenon continues even after the groove and the hole have been filled, as the plating time becomes longer, the plated film tends to form a rise at the portions of the groove and the hole.
As described above, since the film deposition preferentially takes place in the groove and on the bottom of the hole in the electrolytic plating, the plated film tends to form a rise at the portions of the groove and the hole as the plating proceeds. Such a rise is high on the periphery of the wafer 110, and low in the center portion. The reason for this phenomenon is explained as follows:
In the electrolytic plating, a voltage is applied between the wafer 110 and the anode 132 so that a plating film is deposited on the seed layer 112a. The peripheral portion of the wafer 110 is in contact with the contact electrode 131 with the voltage being applied thereto.
Here, the thickness of the barrier metal 111 and the seed layer 112a is extremely thin and has very high resistance, with the result that the seed layer 112a comes to have an electric potential distribution in accordance with the distance from the contact electrode 131.
As described above, the deposition rate is higher on the peripheral portion of the wafer 110 close to the contact than that in the center portion at the initial stage of plating. Such a difference in the deposition rate is great in the case when the thickness of the plated Cu film formed on the wafer 110 is small. In other words, the difference in the deposition rate is the greatest at the initial stage of plating, and becomes smaller as the thickness of the plated film becomes greater.
In the case when the Cu film is removed by the CMP method, the abrasion time is set so as to remove the peripheral raised portion, with the result that the groove in the center portion and the hole portion tend to be excessively abraded, causing a problem in that a concave dent is formed on the surface of the Cu film (that is, on the surface of the wiring). The resulting problems are that there is an increase in the wiring resistance and that there are great deviations in the wiring resistance.
Moreover, when such a concave dent is formed on the wiring surface, metal tends to remain in a concave section on a upper wiring layer formed thereon, resulting in a problem of short-circuiting in the wiring.
An object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can reduce a difference in the deposition rate of plating between the center portion and the peripheral portion on a substrate.
A semiconductor device in accordance with one aspect of the present invention is provided with a plurality of chip-use element formation areas, each having a conductive layer formed by a plating method, a scribe line areas for dividing the plurality of chip-use element formation areas, and an interconnections being formed in the scribe line area and extended to the vicinity of an end edge of a wafer.
In the semiconductor device in accordance with this aspect of the present invention, the interconnection is formed from the vicinity of end edge of the wafer to which a contact electrode for supplying a voltage to the wafer at the time of plating is connected, to the inside of the scribe line area. The formation of the interconnection in this type makes it possible to reduce the resistance in comparison with a case in which only a thin seed layer and a barrier metal are formed; therefore, it becomes possible to reduce a difference in the electric potential between the center portion of the wafer and the peripheral portion thereof to which the contact electrode is connected. Consequently, the difference in the plating rate between the center portion and the peripheral portion of the wafer at the initial stage of plating, thereby enabling to reduce the occurrence of a dent on the surface of the upper-layer interconnection after the CMP process.
In the above-mentioned aspect, more preferably, the interconnection is formed in a manner so as to extend from side of a first chip-use element formation area to side of a second chip-use element formation area.
In this manner, each interconnection is extended laterally through the scribe line area located beside each chip-use element formation area so that the resistance reducing effect is further improved.
In the above-mentioned aspect, more preferably, the interconnection is allowed to surround the chip-use element formation area.
In this manner, the interconnection is extended and located in a manner so as to surround the periphery of each chip-use element formation area so that the resistance reducing effect is further improved.
In the above-mentioned aspect, more preferably, a test element for testing the characteristics of the element within the chip-use element formation area is further provided, and the test element is placed on the scribe line area.
In this manner, the present invention is also applied to a semiconductor device having a test element.
In the above-mentioned aspect, more preferably, the interconnection is formed so as to have a width greater than a width of cut margin of the scribe.
By increasing the width of the interconnection in this manner, the resistance reducing effect is further improved.
In the above-mentioned aspect, more preferably, a plurality of interconnections are formed, and the plurality of interconnections are laminated in the thickness direction, and electrically connected to one another.
By laminating the interconnections in this manner, the resistance reducing effect can be further improved.
In the above-mentioned aspect, more preferably, a semiconductor substrate having a main surface and an doping area formed in the scribe line area of the main surface of the semiconductor substrate are further provided, and the interconnection is electrically connected to the doping area.
By connecting the interconnection to the doping area, the resistance reducing effect can be further improved.
A semiconductor device in accordance with another aspect of the present invention is provided with a chip-use element formation area having a conductive layer formed by a plating method, a scribe line area formed in a manner so as to surround the chip-use element formation area and a interconnection that is formed in the scribe line area surrounding the chip-use element formation area, and reaches the end edge of the semiconductor chip.
In the semiconductor device in accordance with the above-mentioned aspect of the present invention, since the interconnection is formed in the scribe line area, it is possible to reduce the occurrence of a dent on the upper-layer interconnection surface after the CMP process, in the same manner as the aforementioned aspect. Moreover, since the interconnection is allowed to surround the chip-use element formation area, the resistance reducing effect can be further improved.
In the above-mentioned aspect, more preferably, a test element for testing the characteristics of the element within the chip-use element formation area is further provided, and the test element is placed on the scribe line area.
In this manner, the present invention is also applied to a semiconductor device having a test element.
In the above-mentioned aspect, more preferably, a plurality of interconnections are formed, and the plurality of interconnections are laminated in the thickness direction, and electrically connected to one another.
By laminating the interconnections in this manner, the resistance reducing effect can be further improved.
In the above-mentioned aspect, more preferably, a semiconductor substrate having a main surface and an doping area formed in the scribe line area of the main surface of the semiconductor substrate are further provided, and the interconnection is electrically connected to the doping area.
By connecting the interconnection to the doping area, the resistance reducing effect can be further improved.
According to the present invention, there is provided a manufacturing method of a semiconductor device having a plurality of chip-use element formation areas and scribe line areas for dividing the plurality of chip-use element formation areas respectively, comprising the following steps:
First, a interconnection is formed in a manner so as to extend through the scribe line area from the vicinity of the end edge of the wafer. Then, a plating seed layer is formed on the surface of the wafer so as to contact with the interconnection. A plating process is carried out while applying a voltage from a plating electrode to the plating seed layer and the interconnection so that a plated film is formed on the plating seed layer.
In accordance with the manufacturing method of a semiconductor device of the present invention, the interconnection is formed within the scribe line area from the vicinity of the end edge of the wafer to which the contact electrode for supplying a voltage to the wafer at the time of plating is connected. The formation of the interconnection of this type enables to reduce the resistance in comparison with a case in which only a thin seed layer and a barrier metal are formed; therefore, it becomes possible to reduce a difference in the electric potential between the center portion of the wafer and the peripheral portion thereof to which the contact electrode is connected. Consequently, it is possible to reduce the difference in the plating rate between the center portion and the peripheral portion of the wafer at the initial stage of plating, thereby enabling to reduce the occurrence of a dent on the surface of the upper-layer interconnection after the CMP process.
In the above-mentioned manufacturing method of a semiconductor device, more preferably, the process for forming the interconnection, the process for forming the plating seed layer and the process for forming the plated film are repeated so that a plurality of interconnections are laminated within the scribe line area.
By laminating the interconnections in this manner, the resistance reducing effect can be further improved.
The above-mentioned manufacturing method of a semiconductor device is more preferably provided with a process for forming an doping area in the scribe line area at the main surface of a semiconductor substrate, and the interconnection is electrically connected to the doping area.
By connecting the interconnection to the doping area, the resistance reducing effect can be further improved.
In the above-mentioned manufacturing method of a semiconductor device, more preferably, the doping area is formed by an ion injection process simultaneously as an element-use doping area is formed within the chip-use element formation area.
Consequently, it becomes possible to simplify the manufacturing process.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.